1. Field of the Invention
The present invention provides a thin film insulated gate semiconductor device, and more specifically, it relates to a thin film transistor (TFT) having a large ON current to OFF current ratio (ON/OFF ratio) with particularly low OFF current.
2. Description of the Prior Art
Recently, researches are made on insulated-gate type semiconductor devices having a thin film channel on an insulator substrate. In particular, an extensive study is made on thin film insulated gate transistors, i.e., on so-called thin film transistors (TFTs). Those TFTs are intended for controlling pixels of matrix-structured display devices such as those equipped with liquid crystals. The TFTs are classified according to the type of semiconductor which is used therein. For example, they include amorphous silicon TFTs and polycrystalline silicon TFTs. Particularly at present, more effort is paid on the study of materials which take an intermediate crystal structure between amorphous and polycrystalline. Such materials, which are called semi-amorphous silicon, are believed to comprise small crystals being suspended in an amorphous texture.
In an integrated circuit (IC) based on single crystal silicon, polycrystalline silicon TFT also is employed in the so-called SOI technology, for example, to use as a load transistor in a highly integrated SRAM. In this case, however, an amorphous silicon TFT is very rarely used.
Amorphous silicon in general cannot be applied to rapid TFTs because the electric field mobility thereof is low. In particular, a p-channel TFT (PTFT) is unfeasible because the p-type electric field mobility is extremely low. Accordingly, no complementary MOS (CMOS) circuits can be realized using an amorphous silicon because the PTFT cannot be used in combination with an n-channel TFT (NTFT).
However, because the OFF current of an amorphous semiconductor TFT is small, those TFTs based on amorphous silicon are made the best of in applications such as transistors for active matrices of liquid crystals. In such applications, no rapid operation is required, and a TFT having either of the conductivity types suffices the demand. As the requirement for the TFT for such applications being high charge retention capacity, the above mentioned amorphous semiconductor TFTs are favorably employed.
In the contrary to the amorphous semiconductors, polycrystalline semiconductors have larger field mobility and hence are capable of rapid operation. In a TFT employing a silicon film recrystallized by laser annealing, a field mobility as high as 300 cm2/Vs is obtained. It can be seen that the value above for the recrystallized polycrystalline silicon film is extremely high as compared with that of a MOS transistor having fabricated on an ordinary single crystal silicon substrate, which is about 500 cm2/Vs. Considering that the operation speed of a MOS circuit being fabricated on a single crystal silicon is considerably impaired by the stray capacitance between the substrate and the connections, an extremely high operation speed is expected for the device on polycrystalline silicon because an insulator substrate is used therein.
Furthermore, not only an NTFT but also PTFT can be fabricated using polycrystalline silicon. Accordingly, a CMOS circuit can be constructed as well. For example, in a liquid crystal display device operating on an active matrix mode, not only the active matrix but also the peripheral circuits (such as the driver circuit) can be established using polycrystalline TFTs in CMOS circuits, thereby giving a so-called monolithic structure.
The TFTs for use in SRAMs also make the best of the same advantage. The PMOS are constructed with the TFTs to use as the load transistor.
However, as compared with the amorphous TFTs, polycrystalline TFTs in general suffer a higher OFF current because of the larger field mobility, and hence are inferior in retaining the pixel charges in an active matrix. This disadvantage has not been regarded as a serious problem in the conventional matrix having a pixel size of several hundreds of micrometers square, however, with increasing elaboration and fineness of the pixels, the pixel capacitance decreases to make a stable and static display unfeasible.
Furthermore, the source and drain regions (referred to simply as xe2x80x9csource/drain regionsxe2x80x9d or collectively, as xe2x80x9ca source/drain regionxe2x80x9d) cannot be established on an ordinary amorphous TFT by a self-aligning process as those commonly used in the single crystal integrated circuit (IC) technology. This leads to the problem of stray capacitance which generates by geometrical superposition of the gate electrodes and the source/drain regions. On the contrary, the self-aligning process can be applied to polycrystalline TFTs and hence the stray capacitance can be suppressed low.
More specifically, a conventional TFT comprises, as shown in FIG. 2, a substrate 201 having established thereon a source region 204, drain region 202, and a channel region 203, all at about the same thickness. In a TFT having fabricated by a self-aligning process, the channel region (activated layer) 203 is established at approximately the same shape as that of the gate electrode 205. A interlayer insulator 206, as well as drain and source electrodes 207 and 208, respectively, are also provided in the TFT as shown in FIG. 2.
The conventional polycrystalline TFTs are advantageous in some aspects as described above, but there are also some disadvantages that are pointed out. With respect to the problem of OFF current, several measures are proposed to present. One of such countermeasures is to reduce the thickness of the activated region. It has been reported that the OFF current can be reduced by establishing a thinner activated region. For example, it is reported that a channel region having a reduced thickness of 25 nm can suppress the OFF current to 10xe2x88x9213 A or lower. However, it is extremely difficult to crystallize the thin semiconductor film because the film would not readily crystallize. That is, an activated region (channel region) having a sufficiently high crystallinity to realize a practically useful field mobility requires annealing at a high temperature or annealing for a long duration. If a high temperature annealing were to be applied, a heat-resistant substrate such as of quartz is necessary. However, a quartz substrate is expensive, and particularly so for a large area quartz substrate. The use of a large-area quartz substrate is therefore economically disadvantageous. If an annealing for a long duration were to be applied, the throughput decreases, and again, the process results in poor economy.
Furthermore, making the activated layer thinner signifies reducing the thickness of the source/drain regions. This arises from the fact that, in a commonly employed fabrication process, the source/drain regions are fabricated at the same time with the activated region. Thinner source/drain regions mean an increase of resistance in these regions. To avoid this increase in resistance, another step for depositing thicker source/drain regions must be added. However, such an additional step is unfavorable from the viewpoint of yield.
Moreover, the present inventors have found that a MOS having fabricated from a TFT with an activated layer of 50 nm or less yields a low threshold voltage. Accordingly, when such TFTs are fabricated into a CMOS, the resulting product would suffer an extremely unstable operation.
If the activated layer is provided thicker, on the other hand, the OFF current increases but not in linear relation with the thickness of the activated layer. Hence, it is expected that the OFF current is increased non-linearly due to some reason. Characteristic curves for TFTs each having a 100 nm thick activated layer are given in FIG. 3(A). The TFT comprises a gate oxide film 150 nm in thickness, and an activated layer having fabricated by low-pressure chemical vapor deposition (LPCVD) process followed by annealing at 600xc2x0 C. for 24 hours. The voltage between the source and the drain is 1 V. It can be seen from FIG. 3(A) that the both ON and OFF currents are large. Moreover, a shoulder-like anomaly can be observed to appear when a reversed bias is applied to the gate electrode.
When the activated layer is thickly provided, a TFT having a high electric field mobility results because a favorable crystallinity is obtained for the activated layer. No special high temperature annealing or long annealing is necessary in this case. As a result of the study of the present inventors, it has been found that the majority of the OFF current in the thick activated layer flow via the substrate side of the activated layer like flowing through a by-path. The flow path is indicated with an arrow 209 in FIG. 2. The ON/OFF ratio of a TFT can be expressed ideally by ION/IOFF, where ION and IOFF each represent the ON and OFF currents, respectively. When there is a leakage current ILK which flows through a by-path almost independently to the gate voltage, the ON/OFF ratio is expressed by (ION +ILK)/(IOFF+ILK) In practice, ILK is estimated to be far larger than IOFF, but smaller than ION. Hence the apparent ON/OFF ratio is expressed by ION/ILK. It can be seen that the ON/OFF ratio, which is an important index for a TFT, appears to be extremely reduced in this case.
The leakage current above in general occurs by the following two reasons. One is the poor crystallinity of the activated layer on the substrate side. Too many grain boundaries in this side of the activated layer generate many trap levels that the charge migrates by hopping along these trap levels. Since the trap levels are present irrespective of the presence of a gate voltage, they permanently serve as offset current sources. Theoretically, this problem can be overcome by optimizing the conditions for crystal growth, but with a great difficulty.
The other problem resides on the activated layer being rendered conductive on the substrate side because of the movable ions, such as sodium and the like, which have been incorporated into the activated layer from the substrate side. This problem can be solved by increasing the cleanness of the process.
Even if the problem of the leakage current were to be overcome by either of the measures above, the OFF current increases ohmically when the channel layer (activated layer) is thick. On the contrary, the resistivity of the source/drain is sufficiently small because the thickness thereof is thick enough.
A TFT ideally is expected to have a high field mobility and a low resistivity for the source/drain. The OFF current is preferably small. However, a complicated process should not be incorporated into the fabrication. The present invention has been accomplished with an aim to overcome the problems mentioned hereinbefore, and to provide a nearly ideal TFT.
Accordingly, the present invention provides a TFT which utilizes only the preferred portions of the activated layer as the channel; the substrate side of the activated layer, i.e., the side having inferior characteristics because of the poor crystallinity, the remaining movable ions, etc., is left over.
More specifically, the substrate side of the activated layer is fabricated with a semiconductor material having a larger band gap and a smaller mobility than the other side of the activated layer, i.e., the gate insulator side, so that this portion may not function substantially as a channel. Then, the leakage current can be reduced considerably in this region having a large band gap. The other side of the activated layer, i.e., the gate insulator side is constructed with a semiconductor having large mobility and a crystalline structure, which may be any of the semi-amorphous, polycrystalline, and single crystal semiconductors. These semiconductors are referred hereinafter collectively as crystalline semiconductors.
A semiconductor device in accordance with the present invention comprises:
a substrate having an insulating surface;
a pair of source and drain regions provided on the surface of said substrate;
a semiconductor layer extending between said source and drain regions and having a first region where the first region functions as a channel; and
a gate electrode adjacent to said semiconductor layer with an insulator therebetween,
wherein said semiconductor layer includes a second region adjacent to said first region so that the first region intervenes between the insulator and the second region and the second region has a lower orderliness than said first region.